1) Technical Field of the Invention
The present invention relates to a semiconductor device and a manufacturing process thereof, and in particular, relates to so-called a multi-chip-package semiconductor device integrating a plurality of chips within one package and the manufacturing process thereof.
2) Description of Related Arts
Recent innovation of many electrical apparatuses in downsizing and multi-functioning also demands downsizing and multi-functioning of semiconductor devices incorporated in the electrical apparatus. To satisfy this demand, various semiconductor devices have been proposed, including a semiconductor device having a single semiconductor IC chip integrating a memory circuitry and a logic circuitry. Alternatively, a technique well known as a System in Package (SiP) has been developed, in which a memory IC chip and a logic IC chip are integrated within a single package.
The semiconductor IC chip having a plurality of circuitries serving different functions requires, when compared with a mono-functioning IC chip, a more prolonged design period and a more extended production line for various steps of the manufacturing process, thereby causing the production yield to be reduced. Also, the multi-functioning semiconductor IC chip has, in general, a chip surface that becomes wider than the mono-functioning chip.
Meanwhile, the above-referenced conventional SiP technology proposes, for example, the semiconductor device including a plurality of semiconductor chips arranged in parallel on a printed circuit board. However, those semiconductor chips which are arranged in parallel on the board and molded with resin also prevents the package size of the semiconductor device, i.e., the mounting area of the semiconductor device to the board from being reduced.
In addition, many other semiconductor devices are well known, which has one semiconductor chip mounted on another semiconductor chip by means of the SiP technology. For example, the Japanese Patent Application No. 11-288977 illustrates, in FIG. 1, a stacked chip 11 including a semiconductor chip 3 with a memory circuitry 8 stacked on a semiconductor chip 1 with a logic circuitry 3. Also, FIG. 3 shows that the stacked chip 11 is mounted on a board 12 and an insulating resin is molded fully covering the stacked chip 11. Further, in FIG. 5, the stacked chip 11 is mounted on a plurality of inner leads 18 and also the insulating resin is molded that wholly encompasses the stacked chip 11.
However, in case where one (upper) semiconductor chip is mounted on another (lower) semiconductor chip, the chip size of the upper semiconductor chip has to be smaller than the bonding pad region of the lower semiconductor chip, thus, the upper semiconductor chip has a constraint in the chip size. Also, as the number of semiconductor chips molded in the semiconductor device increases, the semiconductor device may totally be condemned at a final inspection step even if only one of the semiconductor chips fails. This reduces the production yield of the semiconductor device thereby to raise the manufacturing cost thereof.